1. Field of the Invention
The present invention relates to semiconductor devices and methods of manufacturing the same and, more particularly, to a semiconductor memory device and to a method of manufacturing the same.
2. Description of the Related Art
The design rules of semiconductor memory devices have been continuously reduced. As design rules become smaller, the area of each unit memory cell becomes smaller. In particular, when an area of a memory cell is reduced, the critical length (CD) of the bottom of a capacitor is also reduced. A reduction in the CD of the capacitor bottom creates a need to fabricate a COB cell structured semiconductor that has sufficiently large capacitance and which does not fall down.
Many capacitors structures have been proposed to increase the capacitance of a capacitor. Among the proposed structures is a capacitor with a cylindrical lower electrode. Such a structure has been widely used because both its inner and outer surfaces can be used as effective areas. However, as design rules decrease, the CD of a cylindrical capacitor decreases and its height increases.
FIG. 1 illustrates, as an example, the equivalent circuit of a semiconductor dynamic random access memory (DRAM). Referring to FIG. 1, 2-bit memory cells share a bit line BL. Gate electrodes G of adjacent transistors are connected with each other via a word line WL. The WL can also be called a gate line. Each memory cell is comprised of a transistor and a capacitor C. Here, the gate and source/drain of the transistor are indicated with G and S/D, respectively.
FIGS. 2A through 5D show a conventional semiconductor memory device that can be represented by the equivalent circuit of the memory cell shown in FIG. 1 and these figures also show a method of fabricating such a circuit. In detail, FIGS. 2A, 3A, 4A, and 5A are plan views of the semiconductor memory device and the other drawings are cross-sectional views thereof. In the plan views, some elements, such as an interlevel dielectric layer, are omitted. Also, the elements newly formed in each process step are illustrated with hatched lines to be distinguished from the existing elements.
Referring to FIGS. 2A through 2D, an isolation region 104 is defined in a semiconductor substrate 100 using conventional device isolation techniques, e.g., trench isolation. Those portions of the semiconductor substrate 100 isolated by the isolation region 104 are active areas 102. S/D denotes a portion of the active area 102, in which source/drain regions will be formed. FIGS. 2B, 2C, and 2D are cross-sectional views of the semiconductor memory device of FIG. 2A, taken along lines I–I′, II–II′, and III–III′, respectively.
The memory cell of the semiconductor memory device shown in FIGS. 2A through 2D is characterized by S/D portions that are arranged a straight line in the length and width directions. The active area 102 is defined such that channels of the transistor are at right angles to a gate line. Such an arrangement is different from an arrangement in which the S/D portions are disposed in a zigzag pattern or in which the channel regions of transistor are disposed in an oblique line with respect to a gate line. The arrangement of the S/D portions and the transistor channels, shown in FIGS. 2A through 2D, is frequently adopted because they help increase the integration of a semiconductor memory device and they help the electric characteristics of the transistors.
FIG. 3A is a plan view of a structure including gate line structures 112, first contact pads 114, and second contact pads 116. FIGS. 3B through 3D are cross-sectional views of the structure of FIG. 3, taken along lines I–I′, II–II′, and III–III′, respectively.
First, the gate line structures 112 are formed on the semiconductor substrate 100. The gate line structure 112 may include a gate dielectric layer formed of a material such as oxide, a conductive layer, a hard mask layer, and a sidewall spacer. During and/or after manufacture of the gate line structure 112, source/drain regions 105 and 106 may be formed in the active areas 102 using ion implantation. Next, a first interlevel dielectric layer 118 is deposited and planarized, and then, first contact holes (not shown) are formed. The first contact holes may be formed using a self aligned contact (SAC) method. Next, the first contact holes are filled with a conductive material and the conductive material is planarized so as to form the first and second contact pads 114 and 116. The first contact pads 114 are connected to the source/drain regions 105 and the second contact pads 116 are connected to the source/drain regions 106.
Referring to FIG. 3B, the first contact pads 114 are disposed such that the distance between adjacent first contact pads 114 is relatively large, e.g., about 1.5 pitch, in the width direction, i.e., perpendicularly to the gate line structure 112. A second contact pad 116 is positioned between adjacent first contact pads 114. Referring to FIG. 3C, the distance between adjacent first contact pads 141 is 0.5 pitches in the length direction, i.e., parallel to the gate line structure 112. That is, the first contact pads 114 are more densely arranged in the length direction than in the width direction.
FIG. 4A is a plan view of a structure stacked with bit line contact plugs 126, bit line structures 132, and storage node contact plugs 136. FIGS. 4B through 4D are cross-sectional view of the structure of FIG. 4A, taken along lines I–I′, II–II′, and III–III′, respectively.
First, the structure of FIG. 4A is made by depositing a second interlevel dielectric layer 122 on the first interlevel dielectric layer 118 covering the first and second contact pads 114 and 116. The deposited second interlevel dielectric layer 122 is planarized. Next, the second interlevel dielectric layer 122 is patterned to form second contact holes (not shown) in a region in which bit line contact plugs 126 will be formed. The second contact pads 116 are exposed through the second contact holes. Thereafter, the second contact holes are filled with a conductive material to form the bit line contact plugs 126.
Next, the bit line structures 132 are formed on the bit line contact plugs 126 so that the bit line structures 132 are connected to the bit line contact plugs 126. The bit line structures 132 are perpendicular to the gate line structures 112. In general, a lower cross-section of the bit line structure 132 is covered with a conductive layer, i.e., the lower conductive layer, and its upper cross-section is covered with a hard mask layer. The lower conductive layer may be formed by patterning the conductive material on the second interlevel dielectric layer 122 during manufacture of the bit line structures 132. In general, the hard mark layer is formed of an insulating material with a high etching selectivity against the second interlevel dielectric layer 122 and a third interlevel dielectric layer 134.
Next, the third interlevel dielectric layer 134 is deposited on the second interlevel dielectric layer 122 and the bit line structures 132 and then is planarized. Then, the second and third interlevel dielectric layers 122 and 134 are patterned to form third contact holes (not shown). Through the third contact holes, the first contact pads 114 are exposed. Like the first contact pads 114, the third contact holes are arranged straight to prevent the second contact pads 116 from being exposed through the third contact holes in the second and third interlevel dielectric layer 122 and 134.
Thereafter, the third contact holes are filled with a conductive material and node separation is performed thereon so as to obtain the storage node contact plugs 136. As a result, as shown in FIG. 4A, the storage node contact plugs 136 are formed in a straight line in the length and width directions, the storage node contact plugs 135 being arranged more densely in the width direction than in the length direction.
For simplicity, the storage node contact plug 136 covered with the second interlevel dielectric layer 122 is hereinafter referred to as a lower storage node contact plug 136a and the storage node contact plug 136 covered with the third interlevel dielectric layer 134 is hereinafter referred to as an upper storage node contact plug 136b. 
FIG. 5A shows a plan arrangement view of capacitor lower electrodes 142. FIGS. 5B through 5D are cross-sectional views of the structure of FIG. 5A, taken along lines I–I′, II–II′, and III–III′, respectively.
A method of fabricating the capacitor lower electrodes 142, shown in FIG. 5A, of a cylindrical capacitor will now be described. First, an etch stopper (not shown) and a mold insulating layer (not shown) are sequentially formed on the resultant structure. Next, the mold insulating layer is etched using a photolithographic process and the exposed etch stopper is removed so as to define an area in which the capacitor lower electrodes 142 are to be formed. Next, a conductive layer (not shown) is conformably deposited on the resultant structure using a material for the capacitor lower electrodes 142, e.g., a polysilicon material or a metal material. Then, a buffer insulating layer (not shown) is deposited on the conductive layer. Next, the buffer insulating layer is etched through dry etch back or chemical mechanical polishing (CMP) and nodes of the conductive layer are separated from each other so as to form the capacitor lower electrodes 142. Next, the remaining buffer insulating layer and mold-insulating layer are removed to obtain the cylindrical capacitor lower electrodes 142.
As described above, conventionally, the storage node contact plugs 136 are arranged densely in a straight line in the length direction. Therefore, the capacitor lower electrodes 142 connected to the storage node contact plugs 136 are also arranged densely and in a straight line in the length direction. The capacitor lower electrode 142 has either a rectangular shape whose length and width are substantially different from each other, or an oval shape, the lengths of whose long axis and short axis are substantially different from each other (see FIG. 5A).
If the capacitor lower electrodes 142 are rectangular (or oval) and cylinder shaped and there is, in the case of a DRAM, a design rule of 0.10 μm, the length of the rectangular cylinder (or the length of the long axis of the oval cylinder) is about 300 nm, its width (or the length of the short axis of the oval cylinder) is about 120 nm, and its height is about 1500 nm. That is, the ratio of the height of the capacitor lower electrode 142 to its length is about 1:5. However, the ratio of the height to the width is 1:12 or more. Also, the distance between adjacent capacitor lower electrodes 142 is just 80 nm in the length direction.
As the height of the capacitor lower electrode 142 increases, it is more likely that the capacitor lower electrode 142 will fall down in the length direction. Also, since the distance between adjacent capacitor lower electrodes 142 in the length direction is very small, it is more likely that adjacent capacitor lower electrodes 142 will connect to each other and that the connection causes a 2-bit failure. This may occur even when one of the capacitor lower electrodes 142 is inclined to a small degree in the length direction.
Further, when the design rule of a semiconductor memory device is 0.10 μm or less, the distance between the third contact hole(s) and/or the capacitor lower electrode(s) 142 is small, and therefore, ArF equipment and an ArF photo resist are required during a photolithographic process. However, the use of the ArF equipment and ArF photo resist increases manufacturing costs and reduces a process margin.